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Inference Architecture & Hardware Dynamics
The Mathematics of LLM Inference: Memory Bandwidth vs Compute Bound
When serving Large Language Models in production, system architects face a fundamental hardware reality: **token generation is almost entirely memory bandwidth-bound, not compute-bound**.
Generating a single output token requires transferring all model weights from High-Bandwidth Memory (HBM or VRAM) to the compute cores. For a 70-billion parameter model running in FP16 precision (140 GB of weights), producing one token mandates reading 140 GB of memory. On an NVIDIA H100 SXM5 with 3.35 TB/s of memory bandwidth, the theoretical peak generation rate is:
Throughput = Memory Bandwidth / Model Weight Size = 3,350 GB/s / 140 GB ≈ 24 tokens/second (single stream)
To reach 500+ TPS on Llama 3.3 70B, providers like Groq utilize specialized Language Processing Units (LPUs) with hundreds of megabytes of ultra-high-speed on-chip SRAM (yielding up to 80 TB/s of internal bandwidth across networked racks), while Cerebras utilizes wafer-scale silicon where the entire neural network resides on-chip without DRAM bottlenecks.
TTFT vs TPS: Which Metric Dictates Your Application Performance?
Understanding the dual phases of LLM inference is essential for system sizing:
- Time To First Token (TTFT - Prefill Phase): The time elapsed from sending the prompt to receiving the very first streaming token. This phase is compute-bound ($O(N^2)$ attention matrix calculation over input tokens). Low TTFT (<150ms) is mandatory for interactive conversational voice bots, search autocomplete, and low-latency agent loops.
- Tokens Per Second (TPS - Decode Phase): The sustained velocity of token generation after the first token arrives. This phase is memory-bound ($O(1)$ memory access per autoregressive token). High TPS (100–1,500 tok/s) is critical for automated code generation, complex reasoning chains (DeepSeek R1 thinking traces), and large document summarization.
Speculative Decoding & Quantization Strategies
To shatter standard memory bandwidth limits, modern inference engines deploy **Speculative Decoding** and **FP8/INT4 Quantization**:
- Speculative Decoding: A small, ultra-fast "draft model" (e.g. Llama 3.1 8B) generates candidate tokens in parallel, which are verified by the larger target model (Llama 3.3 70B) in a single forward pass, yielding a 2.2x–3.5x speedup with zero quality degradation.
- GGUF & AWQ Quantization: Compressing weights from 16-bit to 4-bit (e.g. Q4_K_M) cuts the memory footprint by 70%, allowing models like Qwen 2.5 Coder 32B (20 GB VRAM) to fit on a single consumer NVIDIA RTX 4090 (24 GB VRAM) while maintaining 99% of FP16 coding accuracy.
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Secure Your Nodes →Frequently Asked Questions: AI Inference Speed & Latency
What is a good TPS (Tokens Per Second) speed for AI applications?
For interactive user-facing chat, human reading speed is roughly 5–8 tokens per second, so anything above 30 TPS feels instant. However, for real-time voice agents, coding assistants (Cursor, Windsurf), and multi-step agentic reasoning, speeds of 100 to 500+ TPS are critical to prevent noticeable latency bottlenecks during long generation loops.
Why does Time To First Token (TTFT) vary between providers for the same model?
TTFT depends on prompt caching, queue depth, and prefill hardware FLOPS. Providers that cache prompt prefixes (system prompts, large repositories) can skip the prefill computation, slashing TTFT from 800ms to under 100ms. Conversely, during high cluster load, queuing delays can spike TTFT significantly.
How much VRAM do I need to run DeepSeek R1 locally?
The full DeepSeek R1 671B model requires ~1,340 GB in FP16 or ~404 GB in Q4_K_M quantization, requiring multiple enterprise GPU nodes (e.g. 8x NVIDIA H100 80GB or dual Mac Studio M2 Ultra with unified memory). However, distilled versions such as DeepSeek-R1-Distill-Qwen-32B require only ~20 GB VRAM in Q4_K_M, fitting comfortably on a single NVIDIA RTX 4090 24GB.
Does quantizing a model from FP16 to INT4 reduce inference latency?
Yes. Because token decode is memory bandwidth-bound, halving the weight precision (from 16-bit to 4-bit) means transferring 75% fewer bytes per token from VRAM, leading to a direct 2x to 3x increase in generation throughput on memory-constrained GPUs.